Xilinx’s Versal AI Edge Blends the Border Between Programming and EEs
Wrapping up a two-part series on the new Versal AI Edge series ACAP from Xilinx, AAC talks about the intersection of engineering disciplines and ACAP applications.
As the requirements and applications for technology grown, so has an engineer's job scope. The divides that once existed between other disciplines have quickly become foggy, whether between programming, biology, etc. With this in mind, it becomes a question of where are the boundaries and what support exists for EEs when traversing this middle ground?
One device playing within those boundaries of programming and electrical engineering is Xilinx's new chipset in its adaptive compute acceleration platform (ACAP), the Versal AI Edge series.
After talking with Rehan Tahir, Senior Product Line Manager for the Versal AI Edge series last week, it became necessary to expand even further beyond the initial overview article.
The Versal AI Edge Series chip. Image used courtesy of Xilinx
This article will intend to explore the different applications of Versal AI Edge; however, before diving into that, it is necessary to have a conversation about the shifting border between electrical engineering and programming.
Programming: Not Just For Programmers?
Traditional EE curriculum focuses on diverse principles in the freshman year, including engineering mechanics, mathematics, physics, and science, usually chemistry. Furthermore, as technology advances, the electrical engineering field becomes more specialized over time (splitting engineers in power, radio, analog or digital, and embedded disciplines).
The Versal AI Edge is a triple discipline device that requires skills in programming Arm Cortex processors, FPGA fabric, and AI algorithms.
Utilizing Vitis, Xilinx's unified software platform, engineers can divide the work into discipline-specific tasks using workflows such as Vivado for hardware design, C++ or Python for software, and TensorFlow, Pytorch, and Caffe for AI development.
Three disciplines, one chipset. Screenshot used courtesy of Xilinx
No single designer would be responsible for all three tasks; however, the ability to understand the core principles behind your peers' work will be critical to a project's success.
When considering that, is it time to rethink refocusing the curriculum away from mechanics and chemistry and core skills in AI and real-time operating systems (RTOS)?
Following that question, what applications are expected to use the Versal AI Edge series?
Versal AI Edge Applications: Precision Robotics
In the first two applications covered, designers will see how the entire ACAP device is optimized to serve the problem. Tahir explained how "you need that real-time precision" in a collaborative robotics application (working alongside humans) during our interview.
Specifically, he talks about "how the robot needs to be able to respond to unpredictable movements [of the human]." He says this is where low-latency and machine learning technologies come into the picture.
How an ACAP might be loaded for an industrial robotics application. Screenshot used courtesy of Xilinx
The scalar engine is responsible for actuator controls, cyber-security, safety controls, and user interfaces when it comes to a robotics application. Meanwhile, the adaptable engine handles parallel sensor fusion, and the AI engine enables dynamic executions and predictive maintenance.
What other applications are expected to launch next year, and what benefit does a year bring us in terms of NRE costs?
Versal AI Edge Applications: Autonomous Vehicles
The second application example, the electronic intelligence & control of a vehicle, is one of the hottest topics in the EE field. Again, utilizing the entire ACAP for sensing, thinking, and acting, the Versal AI Edge can process sensor data in parallel and apply AI inferences to action the Arm Cortex RTOS processor for braking, steering, and many other applications.
Flow control for an autonomous vehicle with an ACAP core. Screenshot used courtesy of Xilinx
Xilinx envisions this next-gen ACAP device as the core processor for this application, reducing the need for three Zynq UltraScale+ devices (in Level-3 semi-autonomous driving) down to a single Versal AI Edge.
Xilinx estimates a PCB area reduction of 58%, with increased throughput of 4.4x at the same power envelope as the three Zynq UltraScale+ devices.
Versal AI Edge Applications: Design Considerations with DFx
Xilinx, true to their core, has developed a technology for use in the adaptable engine called dynamic function exchange (DFx), which allows functionality swap within milliseconds.
Dynamic function exchange allows code block changes on the fly. Screenshot used courtesy of Xilinx
Utilizing ROM chips external to the ACAP, new programs can be loaded into active memory via bitstream to facilitate changing conditions, such as autonomous driving.
Autonomous vehicle DFx example. Screenshot used courtesy of Xilinx
Without DFx, a Versal AI Edge designer would have to select the appropriate device based on lookup table (LUT) capacity, which potentially adds cost to the system. Instead, these mode changes allow a richer set of functions to exist without significantly increasing the cost of the ACAP.
Final Thoughts on Preproduction Releases
The Versal AI Edge can be an exciting device for engineers devoted to FPGAs, embedded RTOS, and AI. Although, it might seem slightly premature to announce a device that is nearly a year away from production.
Xilinx appears to have considered this concern as part of its product planning. It suggests that engineers looking to get started on applications for the Versal AI Edge begin on the Versal AI Core Series VCK190 Evaluation Kit. So, if interested, there is a way to start progressing towards the future product release.
Whether you design hardware, work with Arm Cortex MCUs, or focus on AI inferences, the Versal AI Edge ACAP could potentially offer your applications.
What are your thoughts on the upcoming generation of Versal ACAP devices? Do you work on the edge and see the need for this powerful end-point processing power? Let us know in the comments below.