Thomas Keller is the Director of Platforms and Core Technology at u-blox. He learned early in his career that technology development does not always progress in a perfectly straight line. During his PhD studies, he worked on Orthogonal Frequency-Division Multiplexing (OFDM) as a candidate technology for 3G cellular network deployment. OFDM lost that initial tech battle to Code-Division Multiple Access (CDMA) but later returned in LTE cellular systems.
In this fascinating conversation, Keller discusses the challenges facing the industry today as low-power, low-bandwidth, low-cost IoT devices attempt to connect to a 5G network focused on high-power, high-bandwidth, low-latency applications. Interestingly, much of our current 5G networks are still relying upon an LTE backend. What happens when LTE goes away?

The SARA-R5 module series connects IoT devices in the 5G era. Images used courtesy of u-blox and Adobe
In this Moore’s Lobby podcast with our host, Daniel Bogdanoff, Keller offers his thoughts on what should come next and guidance for developers who need to navigate the phase-out of LTE worldwide. This interesting topic deserves thoughtful consideration and impacts system designers and companies across a wide range of industries.
Meet Thomas Keller
Thomas Keller is the Director of Platforms and Core Technology in the Cellular Products Center at u-blox. U-blox develops semiconductor ICs and modules for location and wireless communication. In his role, Thomas provides technical leadership for products that include R5 and S5 LPWA and satellite chipsets. In his role, Thomas provides technical leadership for products that include R5 and S5 LPWA and satellite chipsets.
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Before joining u-blox, Thomas was a Principal Engineer at Research in Motion in Cambridge, UK. He has also worked for Analog Devices and Mediatek as a technical lead and architect for cellular modem development.
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i got some warnings in proteus
ISIS Release 8.13.00 (Build 31525) (C) Labcenter Electr
Compiling design ‘E:\hackranker\led_lpc2138.pdsprj’.
Netlist compilation completed OK.
Pin XTAL1’ is not modelled.
Pin XTAL2’ is not modelled.
▲Pin ‘RTXC1’ is not modelled.
Pin ‘RTXC2’ is not modelled.
Pin ‘IRST’ does not exist in child module.
Pin ‘EN’ does not exist in child module.
Pin ‘100’ does not exist in child module.
Pin ‘102’ does not exist in child module.
Pin VCC’ does not exist in child module.
Pin ‘RXD’ do not exist in child module.
Pin ‘TXD’ does not exist in child module.
Pin ‘GND’ does not exist in child module.
Netlist linking completed OK.
Partition analysis completed OK.
Simulating partition [13280CD2]
PROSPICE 8.13.00 (Build 31499) (C) Labcenter Electron
Loaded netlist ‘C:\Users\ADMIN\AppData\Local\Temp\
Loading HEX file ‘..\k4_project_1.hex’.
Read total of 8356 bytes from file ‘.. \k4_project_1.hex’.
Memory configuration: 512KB ROM, 32KB RAM
Simulation is not running in real time due to excessive CPU