Technical Article

Simulating the Switching Power Dissipation of a CMOS Inverter

May 19, 2024 by Robert Keim

When a CMOS inverter switches logic states, power is consumed due to its charging and discharging currents. Learn how to simulate these currents in LTspice.

The first article in this series explained the two broad categories of power dissipation in a CMOS inverter:

  • Dynamic, which occurs when the inverter changes from one logic state to another.
  • Static, which results from leakage currents that flow during steady-state operation.

We won’t discuss static power dissipation further. Instead, this article and the next one will present SPICE simulations to help you more thoroughly understand an inverter’s different types of dynamic power dissipation. This article focuses on switching power—the power consumed due to capacitive charging and discharging when the output voltage changes.


LTspice Inverter Implementation

Figure 1 shows the basic LTspice inverter schematic that we’ll be using.


An LTspice CMOS inverter.

Figure 1. An LTspice implementation of a CMOS inverter.


In this implementation, we’re using the nmos4 and pmos4 MOSFETs from LTspice’s component library. Specifying the FETs’ length and width is easy—just right-click the circuit symbols and LTspice will open the window in Figure 2.


Specifying dimensions of the inverter's MOSFETs in LTspice.

Figure 2. Specifying MOSFET dimensions in LTspice.


We’re going to be old-fashioned—this process node was introduced in the early 2000s—and use a 90 nm length for both MOSFETs. For the NMOS, I chose a 150 nm width. The PMOS width follows the rule of thumb that says it should be about 2.5 times wider than the NMOS.

The additional width compensates for the lower mobility in a PMOS transistor, helping to equalize the inverter’s rise time and fall time. You can see the falling and rising output transitions in Figures 3 and 4, respectively.


Simulated high-to-low output transition.

Figure 3. High-to-low output transition for the simulated CMOS inverter. The fall time (90% to 10%) is 610 ns.


Simulated low-to-high output transition.

Figure 4. Low-to-high output transition for the simulated CMOS inverter. The rise time (10% to 90%) is 390 ns.


You may have noticed that the rise and fall times for this inverter are not equal, despite what I said above. Instead, the voltage plots record a fall time of 610 ns and a rise time of 390 ns. The NMOS and PMOS transistors in the default LTspice model library have different electrical performance characteristics than I expected. 


Simulating Charging and Discharging Current

A CMOS inverter’s dynamic power dissipation is associated with two types of current that flow during the transitional stage between logic states. In this article, we’re discussing only one: the current required to charge and discharge capacitances. To help us examine this, I’ve added the following to our original schematic:

  • A small capacitor. This represents the load capacitance that must be charged when the output voltage changes.
  • A very large resistor. This represents a high-impedance component that’s connected to the inverter’s output terminal.

The new schematic can be seen in Figure 5. Keep in mind that in a real circuit, the output capacitance isn’t just a single capacitance on the output node. Parasitic and internal capacitances also contribute to the total output capacitance.


LTspice inverter with output capacitance and load resistance.

Figure 5. LTspice inverter with output capacitance and load resistance.


The red trace in Figure 6 shows the current that flows into the VOUT node of this inverter during a low-to-high output transition. I added this to the plot by holding the Alt key and clicking on the wire that leads to C1 and R1. This is a handy LTspice trick that you might not have been aware of—you can measure the current flowing through any section of wire using Alt + click (or Cmd + click, if you’re on a Mac).


Transient current during a low-to-high output transition.

Figure 6. Transient current (the red trace) during a low-to-high output transition.


The steady-state current is negligible on both sides of the transient. Before the transient, it’s basically zero because VOUT is at the ground potential. As VOUT increases, significant current must flow from VDD and through the PMOS transistor to charge C1. After the transient, VOUT reaches its new steady state value at VDD. The current is again extremely low (about 18 nA) because the R1 resistance is so high.

The current in the plot above is reported as positive because LTspice assumes that the current flowing out of the PMOS drain to charge C1 is positive. The next plot (Figure 7) shows a high-to-low output transition. Since the discharging current is flowing in the other direction, it’s reported as negative.


Transient current during a high-to-low output transition.

Figure 7. Transient current (the red trace) during a high-to-low output transition.


As they flow through the resistance of the PMOS or NMOS converter, these transient currents result in energy loss. This loss is explained in the preceding article, “Power Dissipation of a CMOS Inverter.”


Up Next

We’ve looked at schematic design and simulation results for switching currents in a CMOS inverter. In the final installment of this three-part series, we’ll examine short-circuit current. To do so, we’ll employ LTspice’s ability to directly measure instantaneous power.


All images used courtesy of Robert Keim