LFSR Core - Random Number Generator

LFSR Core - Random Number Generator


Category: Arithmetic Core

Created: July 27, 2010

Updated: January 27, 2020

Language: VHDL

Other project properties

Development Status: Alpha

Additional info: Design done

WishBone compliant: No

WishBone version: n/a

License: LGPL


The lfsr core is a random number generator based on linear feedback shift register(LFSR).The sequence generated has the maximum length possible.The period of sequence generated by a n-bit LFSR is equal to 2^n-1.The tap values used are supposed to create maximum length sequence.

The size of LFSR is a generic parameter.
The core is designed in a way such that the seed of the process can be set from outside.
An output enable pin make the output bit to zero's when driven low.

A testbench code is provided along with core.You can use that to verify the results.Also it is advised to create your own testbench code and test the design.If you find any bugs in the design please report them at the Bugtracker section.

Since the sequence generated is not exactly random,please be careful before using this core for cryptographic purposes.

If you find this design useful please send an email to lalnitt@gmail.com.I would very much appreciate it.