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Details
Category: Communication Controller
Created: Aug 23, 2007
Updated: Jan 27, 2020
Language: VHDL
Other project properties
Development Status: Stable
Additional info: Design done
WishBone compliant: No
WishBone version: n/a
License: n/a
Description
A (as far as I know) untested VHDL translation of the Verilog Can protocol Controller
To Download, click at the "Downloads" button upper right part of this page
This project is a translation Igor Mohor's Verilog http://opencores.orgproject,can,overview (CAN Protocol Controller)
Features
The modules have "_vhdl_" added to their names, to ease compare simulation with Verilog version (for those with mixed a language simulator)
Status
use at own risk - have no had time to test/simulate
check the Philips SJA1000 data sheet and the http://opencores.orgproject,can,overview (Verilog project page) for more information
