ARINC 429 Transmitter And Receiver
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Details
Category: Communication Controller
Created: August 15, 2019
Updated: November 19, 2019
Language: Verilog
Other project properties
Development Status: Beta
Additional info: Design done, FPGA proven
WishBone compliant: No
WishBone version: n/a
License: Others
Description
The aim of this project is to provide a set of ARINC-429-compatible TX and RX synthesizable interfaces. The transmitting interface serializes a 32-bit A429 word with the appropriate timing and encoding characteristics whereas the receiving interface samples serialized data, providing the decoded 32-bit words at the output.
