APB SPI Design Transmission

APB SPI Design Transmission


Category: Communication Controller

Created: July 05, 2017

Updated: January 27, 2020

Language: Verilog

Other project properties

Development Status: Planning

WishBone compliant: No

WishBone version: n/a

License: LGPL


APB SPI design is meant to be interfaced with slow-speed peripherals. The initial design will contain APB slave on one side, which will initiate the transactions which can read data from and write data to SPI peripheral. Since SPI is a serial interface, in case of a write, the design will ensure that data obtained through the APB interface is completely transmitted on SPI interface before it initiates a new transaction. Incase of a read, entire data will be collected from SPI side and transmitted on the APB side, before the next transaction starts.

APB always works on a fixed frequency , whereas the frequency of operation of SPI is programmable.

The protocol versions supported by the current design are APB version 2.0[1] and SPI version 3.06[2].

[1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ihi0024cindex.html
[2] https://web.archive.org/web/20150413003534/http://www.ee.nmt.edu/~teare/ee308l/datasheetsS12SPIV3.pdf