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LinkedinSATA PHY Host Controller with AXi Interface
Details
Category: Communication Controller
Created: Jul 12, 2012
Updated: Jan 27, 2020
Language: Verilog
Other project properties
Development Status: Stable
WishBone compliant: No
WishBone version: n/a
License: LGPL
Description
SATA PHY layer which can be implemented as either a host or device for Xilinx 6 series devices.
A host controller core with AXI interface is available, contact me for more information.
