SystemC USB 1.1 Function IP Core

SystemC USB 1.1 Function IP Core


Category: Communication Controller

Created: May 10, 2004

Updated: January 27, 2020

Language: Other

Other project properties

Development Status: Stable

Additional info: Design done

WishBone compliant: No

WishBone version: n/a

License: n/a


This project consists of the translation of the USB 1.1 Function IP Core Verilog code and dependencies, maintained by Rudolf Usselmann, into a Synopsys CoCentric SystemC Compiler compatible SystemC code.
This project is part of the BrazilIP Fenix project.


- Written In SystemC
- Synopsys CoCentric SystemC Compiler Compatibility
- Fully Synthesisable
- 8051 Interface
- OCP Interface
- Test bench is included
- SystemC code: simulation through binary generated by the gcc
- Verilog code: simulation through tools like ModelSim or Icarus (the IP Core Verilog files may be generated by CoCentric SystemC Compiler)


- The translation is done.
- It was verified by simulation with OCP Interface (SystemC and Verilog.)
- It was verified by simulation with 8051 Interface (Verilog.)
- OCP Interface Protocol under verification.
- The hardware verification will be made (XILINX XC2V2000.)
- The XILINX TIMED SIMULATION (Verilog code generated by ISE) in ModelSim is done.


- SystemC v2.0.1 - g++ or Visual C++ Compilers - Synopsys CoCentric SystemC Compiler (optional)