Small 1-wire Master with Altera Tools Integration

Small 1-wire Master with Altera Tools Integration

Details

Category: Communication Controller

Created: July 13, 2010

Updated: January 27, 2020

Language: Verilog

Other project properties

Development Status: Stable

Additional info: Design done, FPGA proven, Specification done

WishBone compliant: Yes

WishBone version: n/a

License: LGPL

Description

This IP implements the 1-wire communication protocol (http://en.wikipedia.org/wiki1-Wire).
A more detailed documentation is provided in "doc/sockit_owm.odt".

RTL features:
- small RTL, should fit into a CPLD
- Avalon MM bus, Wishbone compatible with a simple adapter
- timed reset, presence, write/read bit transfers
- overdrive
- power supply (strong pull-up)

SOPC Builder integration

Nios II EDS integration:
- port of the 1-wire open domain kit version 3.10b
- interrup driven or polling driver
- uCOS-II support (only partialy tested)


The source code and documentation are available on github:
https://github.com/jerassockit_owm