Pipelined Wishbone Bus to AXI Converter

Pipelined Wishbone Bus to AXI Converter


Category: Communication Controller

Created: September 06, 2016

Updated: January 27, 2020

Language: Verilog

Other project properties

Development Status: Stable

Additional info: Design done, FPGA proven

WishBone compliant: Yes

WishBone version: B.4

License: GPL


Built out of necessity, this core is designed to provide a conversion from a wishbone bus to an AXI bus. Primarily, the core is designed to connect a wishbone bus, either 32 or 128 bits wide, to a 128-bit wide AXI bus, which is the natural width of a DDR3 transaction. Hence, if the Memory Interface Generated DDR3 controller is running at a 4:1 clock rate, memory clocks to AXI system clocks, then it should be possible to accomplish one transaction per clock at a sustained or pipelined rate. This bus translator is designed to be able to handle one transaction per clock.

A second bridge has since been added to the repository. This bridge converts AXI4 (full, not lite) to wishbone B4/pipeline.

Current Status

The wishbone to AXI4 bridge appears to be working quite well, as I have used it now in practice for several years. I'm sure there's something in there that I'm missing, but for now it has worked in every situation I've tried it within.

The AXI4 to Wishbone bridge has just been added to the repository. It's status is known to be broken. Consider it a work in progress.

I've recently added an AXI-lite to wishbone bridge, and a wishbone to AXI-lite bridge together with the formal properties necessary to verify both of them.

Finally, because I've been struggling to access opencores for updates and more, the repository has been moved to GitHub.


Please contact me at zipcpu (at) gmail.com if you have any questions about these cores.