YANU - Rx/Tx FIFO Buffers State Feature

YANU - Rx/Tx FIFO Buffers State Feature


Category: Communication Controller

Created: June 10, 2009

Updated: January 27, 2020

Language: VHDL

Other project properties

Development Status: Stable

Additional info: FPGA proven

WishBone compliant: No

WishBone version: n/a

License: LGPL



YANU (Yet Another Niosii Uart) has been built from scratch with the efficiency in mind in term of CPU load. A complete uCLinux TTY driver has been developed.
Its main feature is that it has a TX and and RX FIFO buffers with a predictive "event to interrupt" generation.
This will lead to a lower CPU usage needs in high efficiency point to point communication links at high baud rates.
It has a fractional prescaler so that almost any baud rate can be generated from any input clock frequency.
It detects all the common asynchronous errors (Parity,Framing,Overrun).
It is programmable in terms of hardware handshake, number of bits and stop bits; it can generate break conditions, etc...
It has an Avalon compliant bus interface and it has been tested successfully in Altera FPGAs (average logic block usage is 330 logic cells in CycloneIII family).