SPI Master Receiver for ADC (AD747x)

SPI Master Receiver for ADC (AD747x)


Category: Communication Controller

Created: June 14, 2009

Updated: January 27, 2020

Language: VHDL

Other project properties

Development Status: Stable

Additional info: Design done

WishBone compliant: No

WishBone version: n/a

License: LGPL


this core represents an minimalistic SPI receiver for ADC like AD747x.
one have:
- tunable sequence len, loaded data slice of sequence,
- shut-down short sequense generation
- ability continued sequence mode - without frame entry/completing
- ready output for locking received data
- shifht clock output provide ability to build parallel vector receivers by
adding needed shift registers
Syntesis on QuartusII 8.1 Web for EP1C3 16bit sequense with 10 loaded bit ocupies 31 cells