SD & MMC Controller with Wishbone Slave Interface

SD & MMC Controller with Wishbone Slave Interface


Category: Communication Controller

Created: April 11, 2008

Updated: January 27, 2020

Language: Verilog

Other project properties

Development Status: Stable

Additional info: Design done, FPGA proven

WishBone compliant: Yes

WishBone version: n/a

License: GPL


SD (Secure Digital) and MMC memory card controller with Wishbone slave interface. Handles all aspects of card initialization, 512 byte block read, and block write. Hides the complicated SD/MMC memory interface, and presents the user with a simple Fifo interface. Provides transfer speeds up to 24Mbps.
If combined with the fpgaConfig project: http://opencores.orgproject,fpgaconfig
then it is possible to configure an FPGA from SD memory. If the FPGA configuration includes this core (spiMaster) and a softcore processor, then the processor can copy a software image from SD memory into RAM, and then execute from RAM. Thus a complete FPGA softcore processor can be implemented with just an FPGA, DRAM, and SD card.
See fpgaConfig used in a complete project at:


- Simple interface to SD cards up to 2GB
- SD Initialization
- SD 512 byte block write
- SD 512 byte block read
- Data access up to 24Mbps
- 8-bit Wishbone slave interface
- Separate Wishbone and core logic clocks
- Simulation files
- 900 logic cells in Altera Cyclone2


Tested in FPGA.
The following mods and additions could be useful:
- Interrupt line.
- Card detect.
- Master wishbone interface would be nice, so that DMA transfers to memory could be performed.
- SD/MMC memory card simulation model needs improvement. The model does not parse the commands from the core, and does not provide any storage.
- Multiple SPI chip select support.
- Larger Fifos to allow simultaneous processor and core Fifo access.


Release 1.2 now available. New version modifies read timing which was marginal for some SD cards.