Single Slot PCM Interface
Details
Category: Communication Controller
Created: September 17, 2002
Updated: January 27, 2020
Language: Verilog
Other project properties
Development Status: Stable
Additional info: FPGA proven
WishBone compliant: No
WishBone version: n/a
License: n/a
Description
Simple PCM Interface. Allows to interface to such popular devices
like TI DSPs (via McBSP bus) in PCM mode. Of course many more
applications. Very small and simple core.
Features
- Implemented in Verilog
- Frame Start position adjustable
- full 16 bit frames
- 1 Receive holding register
- 1 Transmit holding Register
- Fully Synthesisable
- Can handle PCM streams at any rate, 128KHz to 100MHz.
- 38 LUTs in a Spartan II
Status
This core is fully functional and completed. It was tested on
a XESS XCV800 board interfacing to a proprietary device with
a TI DSP, exchanging PCM streams in both directions.
This IP Core is provided by:
www.ASICS.ws - Solutions for your ASIC/FPGA needs -
