16550/16750 UART Compatible Core
Details
Category: Communication Controller
Created: January 14, 2009
Updated: January 27, 2020
Language: VHDL
Other project properties
Development Status: Stable
Additional info: Design done, FPGA proven
WishBone compliant: No
WishBone version: n/a
License: LGPL
Description
Implements a 16550/16750 UART core.
Features
- Full synchronous design
- Pin compatible to 16550/16750
- Register compatible to 16550/16750
- Baudrate generator with clock enable
- Supports 5/6/7/8 bit characters
- None/Even/Odd parity bit generation and detection
- Supports 1/1.5/2 stop bit generation
- None or 16/64 byte FIFO mode
- Receiver FIFO trigger levels 1/4/8/14/16/32/56
- Control lines RTS/CTS/DTR/DSR/DCD/RI/OUT1/OUT2
- Automatic flow control with RTS/CTS
- All interrupt sources/modes
Status
- Test script creation done, should cover most functions
- Test log file available
The core was synthesized on a Altera Cyclone II, connected to x86
standard hardware and than tested with standard OS drivers from:
- Linux 2.2/2.4/2.6
- Windows 2000/XP/Vista
- *BSD
- *DOS
Simulation
It's possible to simulate and test the design with GHDL.
A Makefile is available for starting the simulation. The testbench
creates a log file (uart_log.txt).
Resource usage
- Altera Cyclone II
- 440 LE
- 1216 memory bits
- Frequency: 130 MHz
- Xilinx Spartan 3E
- 378 Slices
- 1 RAMB
- Frequency: 100 MHz
