USB Host Controller Full-Speed
Details
Category: Communication Controller
Created: July 12, 2015
Updated: January 27, 2020
Language: Verilog
Other project properties
Development Status: Stable
Additional info: Design done, FPGA proven, Specification done
WishBone compliant: No
WishBone version: n/a
License: GPL
Description
USB 1.1 Host Controller
This IP core is a cutdown USB host controller which allows communications with full-speed (12mbps) USB devices.
The IP is accessed via an AXI4-Lite slave register interface for control, status and data.
Data to be sent or received is stored in some internal FIFOs. The data is accessed through the AXI4-Lite slave port. There is no DMA engine (e.g. a bus mastering interface) associated with this IP.
The core functions well, is very small, but is fairly inefficient in terms of CPU cycles required to perform USB transfers. This core is not compliant with any standard USB host interface specification, e.g OHCI or EHCI.
Instantiation
Instance usbh_host and hookup to UTMI PHY interface and a AXI4-Lite master (e.g. from your CPU). The core requires a 48MHz/60MHz clock input, which the AXI4-Lite and UTMI interfaces are expected to be synchronous to.
Limitations
- Only tested for USB-FS (Full Speed / 12Mbit/s) only.
- AXI4-L address and data must arrive in the same cycle.
Testing
Verified under simulation and on FPGA with various USB devices attached (hubs, mass storage, network devices).
