RC4 Pseudo-random Stream Generator
Details
Category: Crypto Core
Created: May 17, 2012
Updated: January 27, 2020
Language: Verilog
Other project properties
Development Status: Stable
Additional info: Design done, FPGA proven, Specification done
WishBone compliant: No
WishBone version: n/a
License: LGPL
Description
RC4 PRBS (Generates the RC4 stream, then you have to XOR it with your data to crypt or decrypt it), takes 768 clocks to do key-expansion, then start outputting one-byte of random stream for every clock (output_read signals valid output in K). Based on RC4 implementation in wikipedia.
