Fade Light L3 Ethernet PHY Protocol

This project implements the simple and light protocol for transmission of data from low resources FPGA connected to the Ethernet PHY and an embedded system running Linux OS. The main goal was to assure the reliable transmission over unreliable Ethernet link without need to buffer significant amount of data in the FPGA. This created a need to obtain possibly early acknowledgment of received packets from the embedded system, and therefore the protocol had to be implemented in layer 3.
The Ethernet type 0xfade was used (unregistered, but as this protocol should be used only in a small private networks, without routers, with switches only, it should not be a problem).
We assume, that the FPGA is capable to store one "set" of packets (in the example design length of this set is equal to 32). To start the transmission, receiver sends the "start transmission" packet:

TGT,SRC,0xfade,0x0001,pad to 64 bytes

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TGT,SRC,0xfade,0xa5a5,set & packet number, delay, 1024 bytes of data

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TGT,SRC,0xfade,0x0003,set & packet number, pad to 64 bytes

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TGT,SRC,0xfade,0x0005, pad to 64 bytes

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1. set number
2. valid (ready to be sent)
3. sent (has been sent at least once - used for delay adaptation)
4. confirmed (reception has been confirmed, packet may be replaced with the same packet from the next set)

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,http://www.ise.pw.edu.pl/~wzab/fpga_l3_fade,
,http://arxiv.org/abs/1208.4490,
,http://proceedings.spiedigitallibrary.org/proceeding.aspx?articleid=1763152 ,

DISCLAIMER:

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LICENSING:

1. My kernel driver is released under the GPL license
2. My user space application is public domain
3. My FPGA code is published with BSD license
4. The core kept in FPGA_with_MAC directory includes also very slightly modified Ethernet MAC http://opencores.org/project,ethernet_tri_mode which is published under LGPL. (The core located in the FPGA_no_MAC directory does not use MAC core, the Ethernet PHY is controlled directly by simple state machines.)
5. Due to licensing issues I can include only xco files for blocks generated by Xilinx tools

REBUILDING of FPGA CORES

EXPERIMENTAL "JUMBO FRAMES" BASED IMPLEMENTATION FOR 1Gb/s and 10GB/s LINKS

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,Low latency protocol for transmission of measurement data from FPGA to Linux computer via 10 Gbps Ethernet link,