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Grain - A Stream Cipher in VHDL



Grain - A Stream Cipher in VHDL

Details

Category: Crypto Core

Created: Nov 22, 2008

Updated: Jan 27, 2020

Language: VHDL

Other project properties

Development Status: Beta

Additional info: FPGA proven

WishBone compliant: No

WishBone version: n/a

License: LGPL

Description

This project has been MOVED to bitbucket: https://bitbucket.org/vahidigrain