Grain - A Stream Cipher in VHDL

Grain - A Stream Cipher in VHDL

Details

Category: Crypto Core

Created: November 22, 2008

Updated: January 27, 2020

Language: VHDL

Other project properties

Development Status: Beta

Additional info: FPGA proven

WishBone compliant: No

WishBone version: n/a

License: LGPL

Description

This project has been MOVED to bitbucket: https://bitbucket.org/vahidigrain