Sata stack written in Verilog

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Staus:

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Code Organization:

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sata_stack.v (Top File that applications interface with)

sata_defines.v (Set defines for the stack in here)
 

generic/ (small modules used throughout the design)/

blk_mem.v (wraps around an infered block memory generator)

cross_clock_enable.v (simple module that allows users to send enables across a clock domain)

debounce.v (debounce)

ppfifo.v (ping pong FIFO, similar to a ping pong buffer except the user doesn't need to track the addresses)

 

command/

sata_command_layer.v (Sata Command Layer)

 

transport/

sata_transport_layer.v (Sata Transport Layer)

 

link/

sata_link_layer.v (Sata Link Layer)

sata_link_layer_read.v (Sata link layer read side)

sata_link_layer_write.v (Sata link layer write side)

scrambler.v (scrambles/descrambles primitives)

crc.v (Cyclical Redundancy Check/ creator)

cont_controller.v (controls the scrambling of primitives)

 

phy/

sata_phy_layer.v (Sata phy layer)

oob_controller.v (out of band controller)

 

platform/

sata_platform.v (This is a template file you can use to interface with the gigabit transceivers)

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Python

Python pip

Cocotb (Python test bench tool for HDL Projects) Download, build and install Cocotb

Nysa (Required for the SATA driver): pip install git+https://github.com/CospanDesign/nysa

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