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SystemC/Verilog MD5 Hash Core Standard

SystemC/Verilog MD5 Hash Core Standard

Details

Category: Crypto Core

Created: Aug 27, 2004

Updated: Jan 27, 2020

Language: Other

Other project properties

Development Status: Stable

Additional info: FPGA proven

WishBone compliant: No

WishBone version: n/a

License: LGPL

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Description

A SystemC/Verilog synthesizable MD5 hash core.

This work is given by Universidad Rey Juan Carlos (Spain)

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