Pipelined Fixed Point Elementary Functions with CORDIC
Details
Category: DSP Core
Created: December 22, 2013
Updated: January 27, 2020
Language: Verilog
Other project properties
Development Status: Alpha
Additional info: Design done, FPGA proven
WishBone compliant: No
WishBone version: n/a
License: LGPL
Description
Conveyored (result on every clock) elementary functions, implemented with CORDIC for demoscene project (http://www.youtube.comwatch?v=oh1_MzuFtdU). Number sizes in bits parametrized. Tested by eye, on DE2-115 board with VGA display.
Testing environments for DE2-115 and Marsohod II dev. boards included. DE2-115 testing environment may contain some board related code copyrited by Terasic or Altera.
Test projects for DE0 and DE0_nano dev. boards may be added on request.
