Educational Implementable RISC Core Processor
Details
Category: Processor
Created: September 17, 2004
Updated: January 27, 2020
Language: Verilog
Other project properties
Development Status: Stable
Additional info: FPGA proven
WishBone compliant: No
WishBone version: n/a
License: n/a
Description
An implementable and enhancable RISC Core developed in Verilog HDL, tested on Xilinx IIE Spartan FPGA.
Features
- feature1
- feature1.1
-feature1.2
-feature2
Status
-Currently present Verilog Module is implementable, and also enhancements could be made as desired
- status2
