KLC32 32-bit Non-pipelined Processor

KLC32 32-bit Non-pipelined Processor


Category: Processor

Created: October 05, 2011

Updated: January 27, 2020

Language: Verilog

Other project properties

Development Status: Planning

WishBone compliant: No

WishBone version: n/a

License: LGPL


KLC32 is a 32 bit non-pipelined processor. This project is in the first stage of it's evolution and has a long ways to go yet, hence descriptions are a bit lacking. Read the code. First coding was Oct 4, 2011.

Programming Model

There a 32 x 32 bit registers with register R0 always reads as zero.

There are two processor modes, user and system, each with it's own stack pointer. Some instructions are restricted to system mode only.

There is a group of eight condition code registers cr0 to cr7, each of which contains four status flags: carry,overflow,negative, and zero. The compare instruction can set any one of the group of condition codes.
Many instructions update cr0 automatically.

Two address modes are supported: register indirect with displacement, and indexed addressing.