RV01 a two-way in-order superscalar processor for RISC-V Core

RV01 a two-way in-order superscalar processor for RISC-V Core

Details

Category: Processor

Created: December 11, 2017

Updated: January 27, 2020

Language: VHDL

Other project properties

Development Status: Beta

Additional info: Design done, FPGA proven, Specification done

WishBone compliant: No

WishBone version: n/a

License: LGPL

Description

RV01 is a two-way in-order superscalar processor core implementing RISC-V RV32I instruction set with “M” extension according to RISC-V ISA version V2.0, and (with some exception) privileged architecture according to version V1.7. The RV01 core stores instruction and data inside on-chip memory (no cache, no MMU). User-configurable RV01 core features include: instruction/data memory size, scalar/superscalar execution capability, branch/jump prediction, Debug module and PLIC module. "Full-optional" version delivers ~1.8 DMIPS/MHz.