FWRISC - Featherweight RISC-V RV32I Implementation
Created: November 28, 2018
Updated: January 27, 2020
Other project properties
Development Status: Alpha
Additional info: FPGA proven
WishBone compliant: No
WishBone version: n/a
FWRISC is a Featherweight RISC-V RV32I implementation. All instructions and registers are supported.
Source is hosted on GitHub: [Link](http://github.com/mballancefwrisc.git)
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