NEO430 (MSP430-compatible) Customizable Microcontroller-like Processor

NEO430 (MSP430-compatible) Customizable Microcontroller-like Processor


Category: Processor

Created: October 16, 2015

Updated: January 27, 2020

Language: VHDL

Other project properties

Development Status: Stable

Additional info: Design done, FPGA proven, Specification done

WishBone compliant: Yes

WishBone version: n/a

License: LGPL


Welcome to the NEO430 processor project!

You need a small but still powerful, customizable and microcontroller-like processor system for your next FPGA design? Then the NEO430 is the perfect choice for you!

This processor is based on the Texas Instruments MSP430 ISA and provides 100% compatibility with the original instruction set. The NEO430 is not an MSP430 clone – it is more a complete new implementation from the bottom up. The processor features a very small outline, already implementing standard features like a timer, a watchdog, UART and SPI serial interfaces, general purpose IO ports, an internal bootloader and of course internal memory for program code and data. All of the peripheral modules are optional – so if you do not need them, you can exclude them from implementation to reduce the size of the system. Any additional modules, which make a more customized system, can be connected via a Wishbone-compatible bus interface. By this, you can built a system, that perfectly fits your needs.

It is up to you to use the NEO430 as stand-alone, configurable and extensible microcontroller, or to include it as controller within a more complex SoC design.

The high-level software development is based on the free TI msp430-gcc compiler tool chain. You can either use Windows or Linux/Cygwin as build environment for your applications – the project comes with build scripts for both worlds. The example folder of this project features several demo programs, from which you can start creating your own NEO430 applications.

This project is intended to work "out of the box". Just synthesize the test setup from this project, upload it to your FPGA board of choice and start exploring the capabilities of the NEO430 processor. Application program generation (and even installation) works by executing a single "make" command.
NEO430 Overview
NEO430 block diagram, optional modules
are marked using dashed lines
The NEO430 processor features separated internal memories for data and instructions. The size of the instruction memory (IMEM) can be configured to a maximal size of 48kB. This memory can either be implemented as RAM, allowing you to upload new application programs at any time using the bootloader. Also, this bootloader allows to fetch an application image from an external SPI EEPROM at system start-up. By this, you have the advantage of a re-programmable but non-volatile program storage. The internal data memory (DMEM) can have a size of up to 12kB. This program space is used for variables and of course for the heap and the stack of your program. All peripheral devices are memory-mapped and require a special linker script and dedicated C include files to be accessed. Therefore, you need to recompile your programs with the supplied tool chain to make them run on the NEO430.


,For more information about this project and step-by-step tutorials, check out the ,NEO430 Processor Documentary,!,

,This project is also hosted on github.,


Processor Features


  • Open source 16-bit (data and addresses) soft-core processor
  • Very small hardware outline compared to other implementations 😉
  • Full support of the original TI(TM) MSP430 instruction set architecture (ISA) (remove the 's' in https if the page is not loading...)
  • Multi-cycle instruction execution (4..12 cycles per instruction)
  • Software development based on free TI msp430-gcc compiler
  • Application compilation scripts for Windows and Linux/Cygwin
  • C libraries for easy usage of the included hardware modules
  • Execute a single "make" to install your application into the processor's instruction ROM
  • Standard C libraries (like stdlib.c) can be included
  • Many example programs
  • RTL design completely written in behavioral, platform-independent VHDL
  • Exemplary Wishbone memory and switching fabric VHDL components for creating your SoC
  • FPGA-proven design, operating at very high clock speeds
  • Single clock domain for complete processor
  • One user-defined external interrupt request lines
  • Customize the design: Select which optional HW units will be implemented
  • Several integrated modules:
    • Internal instruction memory (IMEM), ROM or RAM, up to 48kB
    • Internal data memory (DMEM), RAM, up to 12kB
    • System information memory (IMEM and DMEM size, clock speed, HW features, ...)
    • Optional multiplier/divider unit (MULDIV)
    • Optional high-precision timer (TIMER)
    • Optional universal asynchronous serial receiver and transmitter (UART)
    • Optional serial peripheral interface (SPI)
    • Optional general purpose parallel IO port (GPIO), 16 inputs, 16 outputs, with pin-change interrupt
    • Optional 32-bit Wishbone bus interface adapter (WB32) - including bridges to Avalon(TM) bus and AXI-Lite(TM)
    • Optional watchdog timer (WDT)
    • Optional cyclic redundancy check unit (CRC16/32)
    • Optional custom functions unit (CFU) for user-defined processor extensions
    • Optional 3 channel 8-bit PWM controller (PWM)
    • Optional two wire serial interface / I2C (TWI)
    • Optional internal bootloader (2kB ROM):
      • Upload program via UART
      • Boot from external SPI EEPROM (like 25LC512)
      • Program the external SPI EEPROM with a boot image
      • Automatic boot process (e.g. no user interaction required to boot from EEPROM)
      • Core hex dump (for debugging or just to see what's going on)
      • Self-explaining serial text console interface

Differences to TI's Original MSP430(TM) Processors


  • Completely different processor modules with different functionality
  • Maximum of 32kB instruction memory and 28kB data memory
  • Specific memory map – included NEO430 linker script and compilation script required
  • Custom binary executable format
  • Only 4 CPU interrupt channels (instead of 16)
  • Single clock domain for complete processor
  • Different numbers of instruction execution cycles
  • Only one power-down (sleep) mode
  • Wishbone-compatible interface to attach custom IP
  • Internal bootloader with text interface (via UART serial port)
  • *NO* built-in support of floating point types (i.e. float & double)


If you are using the NEO430 for some publication, please cite it as follows:

S. Nolting, "The NEO430 Processor",
S. Nolting, "The NEO430 Processor",


If you have any questions about the NEO430 or if you want to give any kind of feedback, feel free to drop me some lines 😉

  • E-mail: