Confluence OpenRisc 1000 32-bit CPU
Details
Category: Processor
Created: April 23, 2004
Updated: January 27, 2020
Language: Other
Other project properties
Development Status: Alpha
WishBone compliant: No
WishBone version: n/a
License: n/a
Description
This is a new implementation of the OpenRisc 1000 architecture in the Confluence language.
Features
- OpenRisc 1000 32-bit CPU
- ORBIS32-I instructions implemented
- Exception handling partially implemented
- C test harness runs S-record programs
- Cache
- Not implemented
- MMU
- not implemented
- Other stuff
- not implemented
News
16 June 04 Upgraded to Confluence 0.9.0
