Leros - 16-bit Tiny Microcontroller Optimized for FPGAs

Leros - 16-bit Tiny Microcontroller Optimized for FPGAs


Category: Processor

Created: September 05, 2011

Updated: January 27, 2020

Language: VHDL

Other project properties

Development Status: Stable

Additional info: Design done, FPGA proven

WishBone compliant: No

WishBone version: n/a

License: BSD


Leros is a 16-bit processor optimized for FPGAs. It consumes less than 200 logic cells and 1-2 on-chip memories.
Leros is programmed in assembler and in a restricted subset of Java. Leros is a direct competitor to tiny processor
cores, such as PicoBlaze.

Comparison with PicoBlaze

Leros targets the same application area as PicoBlaze and
is about the same size. Following list gives the main differences:

* Truly open source (BSD)
* Compiles on Altera and Xilinx tools
* Leros is a 16 bit architectures instead of 8 bit
* Leros has no restrictions on code and data size
* Single clock cycle instructions
* Java based assembler is platform independent
* Simplified Java compiler for Leros available