Potato Processor - Simple RISC-V Processor for use in FPGA Designs
Details
Category: Processor
Created: April 08, 2015
Updated: January 27, 2020
Language: VHDL
Other project properties
Development Status: Alpha
Additional info: Design done, FPGA proven
WishBone compliant: Yes
WishBone version: n/a
License: BSD
Description
Development of the Potato Processor has moved to GitHub, check it out on https://github.com/skordal/potato
Notable features are:
- Supports the full RV32I subset of the RISC-V ISA, version 2.0.
- Supports machine mode as defined by the RISC-V supervisor extensions, version 1.7.
- Provides support for handling up to 8 IRQs without needing a separate interrupt controller.
- Single-cycle execution of all instructions except memory load/store.
- Includes a Wishbone compatible interface for integration into Wishbone-based systems.
The processor has been tested on a Nexys 4 board from Digilent. The design used for testing is included in the source distribution, with instructions on how to get it up and running.
