LXP32 - FPGA-friendly Lightweight Open Source 32-bit CPU Core
Created: February 20, 2016
Updated: January 27, 2020
Other project properties
Development Status: Stable
Additional info: Design done, FPGA proven, Specification done
WishBone compliant: Yes
WishBone version: B.3
LXP32 is a lightweight, open source and FPGA-friendly 32-bit CPU IP core. It uses a simple, original instruction set designed for straightforward FPGA implementation.
- portability (described in behavioral VHDL-93, not tied to any particular vendor);
- 3-stage hazard-free pipeline;
- 256 registers implemented as a RAM block;
- a simple instruction set with only 30 distinct opcodes;
- separate instruction and data buses, optional instruction cache;
- WISHBONE compatibility;
- 8 interrupts with hardwired priorities;
- optional divider.
- synthesizable RTL description;
- automated verification environment (self-checking testbench);
- software tools (assembler/linker, disassembler) with source code.
Note that there's no compiler backend for the LXP32 instruction set architecture yet.
LXP32 Technical Reference Manual
A few commercial precision motor control systems (link in Russian) are powered by the LXP32 processor.
LXP32 is distributed under the terms of the MIT license.