pAVR - 8-bit Controller With 6 Pipeline Stages

pAVR - 8-bit Controller With 6 Pipeline Stages


Category: Processor

Created: January 01, 2003

Updated: January 27, 2020

Other project properties

Development Status: Alpha

WishBone compliant: No

WishBone version: n/a

License: n/a


This project implements an 8 bit controller that is compatible with Atmel's AVR architecture, using VHDL (Very High speed integrated circuits Hardware Description Language).

pAVR is not a specific controller of the AVR family, but rather a maximally featured AVR. It is configurable enough to be able to simulate most AVR family controllers.
The goal was to obtain an AVR processor that is as powerful as possible (in terms of MIPS), with a work budget of about 6 months*man.
pAVR is about 3x faster than the original core, if built with the same technology.

The sources are modularized. They are written starting from a set of common-sense conventions (the process splitting strategy, signals naming, etc)., so that pAVR is quite an easily maintainable design. A comprehensive documentation is provided.

Extensive testing was carried out.


- 6 pipeline stages
- 1 clock/instruction for most instructions
- estimated clock frequency: ~50 MHz & 0.5 um; assuming that Atmel's core runs at 15 MHz & 0.5 um. That's ~3x Atmel original core's performance.
- estimated MIPS at 50 MHz: 28 MIPS (typical), 50 MIPS (peak). That's ~3x Atmel original core's performance. At 15 MHz, Atmel's core has 10 MIPS typical, and 15 MIPS peak.
- CPI (clocks per instruction): 1.7 clocks/instruction (typical), 1 clock/instruction (peak). That's ~0.75x (typical), 1.00x (peak) Atmel original core's performance.
- up to 32 interrupt sources. Each interrupt has programmable priority and jump address.
- heavily parameterized design that permits flexible costumization
- pAVR architecture is rather computational-friendly than control-friendly. Jumps, branches, skips, calls and returns are relatively expansive in terms of clocks. A branch prediction scheme and a smarter return procedure might be considered as upgrades.


Summer 2002: project done.

November 2003: Stefan Kristiansson found a skips-related bug. It's fixed from version 0.33. Thanks Stefan!
A new version is on its way. It's not fully tested tet. Hopefully I'll have time to upload it into an FPGA, and run some heavy weight programs, such as a C compiler.
I am using Xilinx tools: the WebPack free synthesis software, and a Spartan 3 board from NU Horizons.
If you synthesize pAVR and think it would be useful to share your experience with others, you're very welcome to post your results here, in the newly created synthesis page. Just email me at You'll be helping pAVR getting more and more reliable. Thanks.

Autumn 2005: bugs discovered. Changed status from "Stable" to "Alpha". Don't know when I'll have time to debug it :(


For the latest version check here, or my web site.
Note: pAVR's CVS repository is not updated - it contains the ancient version 0.32. I don't plan to use CVS much. Thus, take care to get the latest version from the downloads page, not from CVS repository.