TotalCPU - 12-Bit Instruction RISC Core

TotalCPU - 12-Bit Instruction RISC Core


Category: Processor

Created: June 08, 2007

Updated: January 27, 2020

Language: Verilog

Other project properties

Development Status: Alpha

Additional info: Design done

WishBone compliant: No

WishBone version: n/a

License: n/a


TotalCPU is RISC core with 12-bit instruction width and variable data width (from 12 to 64 bits). It is completely realized on Verilog-2001 and has two variants of implementation - with program counter placed in register block or defined as a standalone register. The first variant requires less hardware resources but it is almost 2 times slower then the second variant. It has its own instruction set that doesn’t depend upon data path width.

the description and sources of TotalCPU are (here)


- Design done