MIPS Takes ‘Software-First Approach’ With New RISC-V NPUs

System designers are rethinking AI inference as software-defined vehicles and autonomous machines continue to push the boundaries of intelligence. MIPS, now part of GlobalFoundries, is targeting that shift with the MIPS S8200, a software-first RISC-V neural processing unit (NPU) designed to enable Physical AI at the autonomous edge.

The MIPS S8200 was recognized as a CES 2026 TechRadar Pro Picks Award winner for its software-first approach to edge AI acceleration. 

The S8200 expands the MIPS Atlas family of RISC-V processor IP and is positioned as the “Think” subsystem within MIPS’ broader Sense-Think-Act-Communicate framework. MIPS is integrating decision-making directly into edge platforms that must sense, reason, and respond in real time.

A Software-First Approach to Edge AI

The S8200 serves as the inference engine for multi-modal, on-device AI workloads. It's designed to complement sensing and actuation components, enabling system-level architectures in which perception, decision-making, and control occur locally. By adding a dedicated NPU optimized for these workloads, MIPS is broadening Atlas from general RISC-V compute into a more complete Physical AI platform.

A defining characteristic of the S8200 is MIPS’ software-first philosophy. Developers can begin model optimization using the Atlas Explorer virtual platform well before silicon is available. This enables hardware-software co-design. This co-design feature allows architects to evaluate performance, power, and latency tradeoffs early in the design cycle. The S8200 supports modern AI frameworks such as PyTorch and TensorFlow through MIPS-optimized compilers and libraries. This supports convolutional networks alongside transformer-class models, which are increasingly common in autonomous perception and decision systems. 

MIPS aims to reduce platform lock-in and lower development costs compared to proprietary AI accelerators by pairing RISC-V’s extensible instruction set with a transparent software toolchain.

Architecture and Key Technical Features

Architecturally, the MIPS S8200 is built from quad-core building blocks with multi-thread support and coherent cluster tiling. This allows designs to scale from tens of TOPS to hundreds of TOPS while maintaining deterministic behavior. MIPS is targeting up to a 4× improvement in TOPS per watt compared to legacy edge architectures, an important metric for thermally and power-constrained systems.

This graphic shows MIPS' 8500 (also in the Atlas family) balancing adaptability against the extremes of uniformity and obsolescence. 

The NPU integrates tightly coupled RISC-V application cores with AI engines. This enables low-latency data exchange between general-purpose processing and inference workloads. Mixed-fidelity support allows designers to balance fast virtual modeling with higher-accuracy simulations as designs mature. The S8200 can be integrated into custom SoCs, reference silicon platforms, or ASIC designs.

Enabling Physical AI at the Edge

MIPS frames Physical AI as the ability for machines to sense their environment, think locally, and act safely without relying on cloud inference. In safety-critical scenarios, milliseconds matter.

For automotive applications, the S8200 is designed to support multi-camera perception pipelines, bird’s-eye-view (BEV) models, and concurrent decision-making tasks for ADAS and autonomous driving. In industrial robotics and AMRs, the platform also supports vision-language-action models that allow robots to interpret natural language, understand context, and manipulate objects in changing environments. Additional target applications include predictive maintenance, quality inspection, medical imaging assistance, and precision agriculture.

With the S8200, MIPS is betting that open, software-first RISC-V architectures can deliver the deterministic, multi-modal intelligence Physical AI demands—without sacrificing flexibility or control.

Early ecosystem adoption is already underway. ForwardEdge ASIC, a subsidiary of Lockheed Martin, has selected the S8200 for a high-performance ASIC aimed at mission-critical autonomous platforms. The S8200 NPU is currently sampling, with MIPS expecting first silicon reference platforms featuring the S8200 in 2027. These platforms are intended to accelerate ecosystem development around RISC-V vector and matrix extensions for autonomous edge applications.

All images used courtesy of MIPS.