QUARK RISK - 8-bit RISC Microprocessor with Wishbone Interconnect for SoC
Details
Category: Processor
Created: February 22, 2016
Updated: January 27, 2020
Language: Verilog & VHDL
Other project properties
Development Status: Planning
WishBone compliant: Yes
WishBone version: n/a
License: LGPL
Description
8bit RISC microprocessor designed with features like wishbone interconnect to provide it as a tool for System-on-Chip or core (ASIC, CISC processor, etc) development decreasing the cost and effort when a bug is present on the design. This processor may be used as core (ASIC, SoC, CISC processor, etc) internal controller(s), so when a bug is present, engineering group shall modify only microcode and reprogram it instead of redesign the HDL modules.
Mechanization Drawing
License Info.
This project is under license LGPL 3.0
LGPL 3.0
