OoOPs - Out-of-Order MIPS (TM) Processor

OoOPs - Out-of-Order MIPS (TM) Processor


Category: Processor

Created: March 24, 2012

Updated: January 27, 2020

Language: Verilog

Other project properties

Development Status: Planning

WishBone compliant: No

WishBone version: n/a

License: LGPL


OoOPs is intended to be a higher-performance alternative to other MIPS(TM)-compatible projects on OpenCores. Many of the other CPU cores are targeted for low resource utilization and/or higher energy efficiency. OoOPs will instead target higher performance (both frequency and IPC) through more aggressive pipelining and out-of-order execution. This means that OoOPs will be more resource intensive, especially due to the nature of out-of-order architectures. To help find better performance/area operating points for the user, many structure sizes and optional features/blocks will be either parametrized or removable through defines.