OpenRisc 1200 HP, Hyper Pipelined OR1200 Core

OpenRisc 1200 HP, Hyper Pipelined OR1200 Core


Category: Processor

Created: October 22, 2010

Updated: January 27, 2020

Language: Verilog

Other project properties

Development Status: Stable

Additional info: Design done

WishBone compliant: No

WishBone version: n/a

License: LGPL


The project is based on OpenCores' OR1200 project.

The core is now hyper pipelined. It is a technique to multiply the functionality
of a design by adding registers (called pipeline stage registers) to the core logic
in order to multiply its functionality. If you are interested in the technology, go to

The functional behavior of the OR1200 remains the same, the hyper pipelined
version is used when multiple OR1200 cores (2, 3, ...) are instantiated in the
same design (multicores).

The main benefit is the multiplication of the core's functionality by only
implementing registers. This leads to a reduced size compared to the
individual instantiation of the cores. This is a great advantage for ASICs
but obviously very attractive for FPGAs with their already existing registers.

Another issue is the performance of the resulting hyper pipelined OR1200 core.
The pipeline stage registers are timing driven placed to partition the critical
path into equal parts, which leads to an almost multiplied performance of the
design. The timing is optimized for a Virtex 5 device from Xilinx.

The modifications are done on RTL, so that the project can be used in an
RTL based testbench.

The project shows the modified RTL code with 2, 3 and 4 times multiplied
functionality. It is delivered with a testbench and a detailed documentation.

Enjoy ...