ARM4U - 5-stages RISC Pipeline ARM Processor Functional Clone
This processor, done as an university project, is a functional clone of the ARM processor, is almost entierely compatible with the ARMv3 instruction set and can be targetted by the GCC toolchain if the proper options are used during the compilation process.
The processor uses a classical 5-stages RISC pipeline and an instruction cache. It was made to connect to the Altera Avalon bus, as a Q-Sys compatible component. It should however be simple to retarget it for other similar buses.
We made it run at 50 MHz on a Cyclone IV FPGA.
Full VHDL sources, schematics and documentation is included.