nCore - 16 Instructions Litle-litle Processor Core

nCore - 16 Instructions Litle-litle Processor Core


Category: Processor

Created: October 27, 2006

Updated: January 27, 2020

Language: Verilog

Other project properties

Development Status: Alpha

WishBone compliant: No

WishBone version: n/a

License: GPL


This is a little-little processor core. It has 16 instructions. It is under developement again, since the latest version is deleted... It is not yet verified, tested, etc.
It's written in Verilog, generaly for Spartan.


-It's very small.
-Easy to understand.
-Easy to convert.
-Easy to compile the RISC or CISC instructions into this small set of commands.


Ver 0.1

Ver 0.2
There was many errors of syntax...
So now there are corrected, it's ready to synthesize.
Not yet wholly tested.

New in downloads:
asm compiler C and Yacc/Lex versions (Alpha)
simple simulator to verify the compiled code
nCore 2: more procedure-capability
nCore 3: safe multi-tasking-capability

Under developement:
C, asm compilers, emulator, BIOS
Under planning:
OS with cooperativ/hybrid multitasking, handling the configuration of the multicore system.