ClaiRISC - Soft MCU Core Runs 12bit Opcode PIC Family
Details
Category: Processor
Created: February 08, 2008
Updated: January 27, 2020
Language: Verilog
Other project properties
Development Status: Stable
Additional info: Design done, FPGA proven
WishBone compliant: No
WishBone version: n/a
License: n/a
Description
This ClaiRISC is a soft MCU core which runs PIC 12bits instruction.Compared with PIC16F57 ,This core has the same number of register file while ports and timer are not avilable,but you can map your device register to the REGINSTER_FILE address.It uses about 240LES in ALTERA CYCLONE device.
Features
- The architecture of ClaiRISC is very clair.
- Written with verilog-2001.
- Two stages pipeline.
- Not support interrupt now.
- Each instruction run in one clock except some "test and skip" instructions which run in two clock.
- Synthesized and tested in ALTERA cyclone device at 50MHZ using 240 LES (4%)and works well.
Legal
I have no idea if implementing this core will or will not violate
patents, copyrights or cause any other type of lawsuits.
I provide this core "as is", without any warranties. If you decide to
build this core, you are responsible for any legal resolutions, such
as patents and copyrights, and perhaps others ....
THIS SOURCE FILE(S) IS/ARE PROVIDED "AS IS" AND WITHOUT ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, WITHOUT
LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
FITNESS FOR A PARTICULAR PURPOSE.
IMAGE: 200735153855.JPG
FILE: 200735153855.JPG
DESCRIPTION: In the name of Leifeng
IMAGE: we.GIF
FILE: we.GIF
DESCRIPTION: Architecture of ClaiRISC
