MicroRISC II 32 Bit 5 Stage Pipeline RISC Processor

MicroRISC II 32 Bit 5 Stage Pipeline RISC Processor


Category: Processor

Created: March 20, 2002

Updated: January 27, 2020

Other project properties

Development Status: Alpha

WishBone compliant: No

WishBone version: n/a

License: n/a


32 Bit RISC Processor, 5 Stage Pipeline. Developed for embedded control of devices. Optimized for the Xilinx SpartanII and Virtex line of FPGA's. Later optimizations will be made for Actel ProASIC(+) FPGA's. Uses the Harvard architecture for memory. It contains one interupt vector with a cause register.

The 5 Stages:
- Fetch
- Decode/Register/Uncoditional Branch
- Execute(ALU/Compare/etc.)
- Memory/Conditional Branch
- Write Back

Unique Instructions:
- Population Count(Ones,Zeros,Bit Changes)
- Random Number Generator


SVN Contains: AU, LU, Compare Unit, Register File, IF, EX, WB Stages

The top level file's really the only thing left. I'm expanding and optimizing many modules and I won't upload them until I am more satisfied with how they function. Also, I may add a few features. I am considering makeing an optional 16 bit ISA.

- AU (Arithmetic Unit) - Missing random number generator
- LU (Logic Unit)
- Compare Unit
- Register File
- Special Instruction Unit(Interupts, Cause Register,Load Low,High)
- Instruction Fetch Stage
- Execution Stage
- Memory Access Stage
- Write Back Stage
Almost Completed:
- Decoder
- Decode/Register Access Stage
- Top Level File