This project was aimed at providing people a simple, runnable, and easy-to-enhance MIPS CPU main architecture, along with well commented Verilog RTL source code, complete simulation test benches & scripts, and detailed documentation. People can read the source code, make simulations to verify the result, and then make modifications to enhance it. I hope this project can help you learning the MIPS CPU architecture and enjoy constructing your own CPU core.
This CPU design is based on Mr. Hu Weiwu’s book ”Computer Achitecture”, Tsinghua University Press, 2011
1. 16-bit data width
2. classic 5-stage static pipeline, 1 branch delay slot, theoretical CPI is 1.0
3. pipeline is able to detect and prevent RAW hazards, no forwarding logic
4. 8 general purpose register (reg 0 is special, according to mips architecture)
5. up to now supports 13 instructions, see ./doc/instruction_set.txt for details
6. Maximum clk Frequency: 82.688MHz on Xilinx 3s1000fg320-5 device (XST).
File system description
+-backend => Backend tool dir
| +-Xilinx => Xilinx ISE work dir
+-bench => Test benches & modelsim scripts for each module
| +-mips_16_core_top => benches & scripts for top module
| +-module_1 => benches & scripts for module_1
| +-module_2 => benches & scripts for module_2
| +-... => ...
| +-module_n => benches & scripts for module_n
+-doc => documentations
+-rtl => RTL source code of this project
+-sim => Modelsim work dir
+-sw => Tool chains
*.asm : => MIPS_16 assembly language source file
*.prog: => MIPS machine language file,
generated from .asm files,
in ASCII format, for simulation only.