K68 - 68k Binary Compatible CRISC Processor

K68 - 68k Binary Compatible CRISC Processor


Category: Processor

Created: February 21, 2003

Updated: January 27, 2020

Language: Verilog

Other project properties

Development Status: Alpha

WishBone compliant: No

WishBone version: n/a

License: n/a


The k68 is a 68k binary compatible CRISC processor. It supports all twelve (12) addressing modes and most of the instructions for a 68000. It has 32-bit external address and data busses. It has eight (8) data and eight (8) address registers where the last address register also acts as a Stack Pointer. It has only one mode of operation and makes no distinction between user mode and supervisor mode.


- Supports all twelve 68000 addressing modes.
- Binary compatible with the standard 68000.
- Capable of executing most 68000 instructions.
- 32-bit external busses.
- 8 Data and 8 Address Registers where the last address register is the SP.
- Single mode of operation, no user and supervisor modes.
- Internal Harvard architecture.
- CRISC Architecture.


- Not optimized. (I figure that the architecture could be further optimized).
- Files available in CVS
- Many unresolved bugs (if you intend to work on it, please email me to get a head start).
- I'm still working on improving it bit-by-bit (pun intended)
- It is prototyped and working on a Spartan2-200 at 20+MHz without hardware MUL/DIV.