aeMB - EDK3.2 Clean Room Implementation Microblaze Core Compatible

Details
Category: Processor
Created: August 10, 2004
Updated: January 27, 2020
Language: Verilog
Other project properties
Development Status: Beta
Additional info: Design done, FPGA proven
WishBone compliant: Yes
WishBone version: n/a
License: LGPL
Description
The aeMB is a clean room implementation of the EDK3.2 compatible Microblaze core using information from the Internet. It is cycle and instruction compatible to the MB for most software commands. It is not meant as a drop in replacement for the Microblaze as it is not 100% architecturally compatible. This is a CPU core that is capable of moving and manipulating data to and from memory. It does not have any peripherals nor interrupt controllers although support for external interrupts is provided. Any peripherals and their respective registers could be mapped to the data memory or FSL memory space. It has a separate instruction, data and FSL buses.
Links
- http://www.petalogix.com/resources/downloadsmb-gcc (Microblaze GCC Toolchain)
- http://www.xilinx.com/ise/embeddedmb_ref_guide.pdf (Microblaze Reference Guide PDF)
- http://en.wikipedia.org/wikiMicroBlaze (Microblaze Wikipedia Entry)
- http://www.itee.uq.edu.au/~jwilliamsmblaze-uclinux (Microblaze uClinux Project)
Notes
Please test it extensively before using. Although every care has been taken to test this core, it is supplied WITHOUT WARRANTY of any kind. If you do find bugs, please feel free to report it using the bug tracker. In order to facilitate debugging, please include any code sequence that is necessary to reproduce the bug. Also, any other information that is necessary will be greatly appreciated.