Sweet32 CPU

Sweet32 is best described as a ‘no-frills’ Minimal-RISC 32bit microprocessor, created by Valentin Angelovski in Melbourne Australia.

Designed with low gate-count in mind, typical Sweet32 logic utilization on the Lattice MachXO2 FPGA (for example), is 842 LUT4 elements in a standard configuration and area-optimized form. Further details can be found in the Sweet32 RISC CPU overview 0v80. HDL sources can be found in the SVN link given above

Sweet32 Architecture Summary:

• 16x32-bit General Purpose CPU registers
• 27 Instructions, Von Neumann and Big-endian oriented core
• 16x16-bit multiplier standard, with optional 32x32-bit multiplier support
• single-cycle external Interrupt channel
• Basic Trace/debug interrupt support included
• Small FPGA Footprint
• Sweet32 minimum-system example includes the following functional elements:
• Sweet32 CPU and BIU (Bus interface unit) running at 33.3MHz and 100MHz respectively
• 4KBytes RAM implemented as Block RAM and can also function as Boot ROM
• 16-bit programmable system timer
• 1 x UART
• 1 x 11-bit sigma-delta ADC input channel
• 2 x 11-bit sigma-delta PWM output channels
• 4-bit User output port
• Sweet32 VHDL is released under LGPL 2.1
• C compiler support effort currently in progress