Tiny64 - 64-Bit RISC CPU with Minimal Resource Usage

Tiny64 - 64-Bit RISC CPU with Minimal Resource Usage

Details

Category: Processor

Created: March 20, 2004

Updated: January 27, 2020

Language: VHDL

Other project properties

Development Status: Stable

WishBone compliant: No

WishBone version: n/a

License: n/a

Description

Description Tiny64

A 64-Bit RISC CPU with minial resource usage. Every opcode is executed in 2 clock cycles.
The word size is configurable via XLEN from 32 up to the FPGA limit. The assembler supports also
differnet word sizes.
Due simplicity TinyX supports no interrupts, cache, MMU, FPU.
Interrupts may supported in the future.

The assembler syntax is unusual. because jump instructions are coded
as MOV to the R7 register.

At March 2004 is was tested 32-Bit and 64-Bit in the Xilinx XC2S200 SpartanII.

Features Tiny64

2 clock cycles on all op-codes
R7, the PC is equal handled like a normal register

Status Tiny64

March, 24th 2004 beta