OpenRISC 1000 Processor Architecture

OpenRISC 1000 Processor Architecture


Category: Processor

Created: September 25, 2001

Updated: January 27, 2020

Language: Verilog

Other project properties

Development Status: Stable

Additional info: ASIC proven, Design done, FPGA proven, Specification done

WishBone compliant: Yes

WishBone version: n/a

License: LGPL


Status of the OpenRISC 1000

The development of the OpenRISC moved to
The files contained in this repository are most likely outdated.
For more information try to get in contact with one of the former developers (project maintainer).