OpenRISC 1000 Processor Architecture
Details
Category: Processor
Created: September 25, 2001
Updated: January 27, 2020
Language: Verilog
Other project properties
Development Status: Stable
Additional info: ASIC proven, Design done, FPGA proven, Specification done
WishBone compliant: Yes
WishBone version: n/a
License: LGPL
Description
Status of the OpenRISC 1000
WARNING!
The development of the OpenRISC moved to OpenRISC.io
The files contained in this repository are most likely outdated.
For more information try to get in contact with one of the former developers (project maintainer).
