MIPS32 Release 1 - 32-bit MIPS Bare-metal CPU Processor
Created: October 14, 2012
Updated: January 27, 2020
Other project properties
Development Status: Stable
Additional info: Design done, Specification done
WishBone compliant: No
WishBone version: n/a
UPDATE 1-Jan-2014: This project has moved to GitHub. Please visit https://github.com/granteamips32r1 for the latest code. No further changes will be committed to this repository.
A 32-bit MIPS processor which aims for conformance to the MIPS32 Release 1 ISA. This processor implementation was designed and built by Grant Ayers as part of the eXtensible Utah Multicore (XUM) project at the University of Utah, 2011-2012. Feel free to send questions or feedback to grant DOT ayers AT stanford.edu.
- Single-issue in-order 5-stage pipeline with full forwarding and hazard detection.
- Harvard architecture with separate instruction and data ports which can be combined if desired.
- All required MIPS32 instructions are implemented, including hardware multiplication and division, fused multiply/adds, atomic load linked / store conditional, and unaligned loads and stores.
- Complete Coprocessor 0 allows ISA-compliant interrupts, exceptions, and user/kernel modes.
- No MMU and no FPU, with toolchain support for software-based floating point.
- Hardware divider is small, multicycle, and runs asynchronously from the pipeline allowing some masking of latency.
- Memory interface is separate from the processor for flexibility with connecting various RAMs.
- Hardware is Big-Endian by default and supports reverse-endian mode for User mode.
- Parameterized addresses for exception/interrupt vectors and boundary address between user/kernel regions.
- Extensive documentation in-source and elsewhere.
- Vendor-independent code.
- A clean, modular design written from scratch.
The project includes a standalone MIPS32 processor as well as a full System-on-Chip design targeted for the XUPV5-LX110T board. With minor changes (clock module, BRAM module, and pin constraints) the SoC can run on many hardware platforms.
The standalone processor utilizes approximately 1,800 slice registers (2%) and 4,000 LUTs (5%) on a Virtex 5 LX110T.
The SoC utilizes approximately 2,700 slice registers (3%) and 5,100 LUTs (7%) on a Virtex 5 LX110T.
1. Add hardware division. (DONE)
The following MMIO hardware drivers are included as part of the SoC design:
- Basic single-master I2C driver.
- 16x2 LCD driver for Sitronix ST7066U, Samsung S6A0069X / KS0066U, Hitachi HD44780, SMOS SED1278, or other compatible hardware.
- LED driver.
- Piezo transducer driver.
- Switch input filter.
- 115200 baud 8-N-1 serial port using only Tx and Rx with configurable baud rate.
- 592 KB BRAM and clock generation for XUPV5 board.
The following software is included:
- XUM bootloader which loads programs from a PC to the FPGA. This is written in C# for Windows, however the boot protocol is simple and can be implemented in any operating system or not used at all.
The software toolchain is based on Binutils, GCC, and Newlib. It can be built for almost any platform, including unix-like environments and Windows (Cygwin). Instructions are included with the project.
The current toolchain uses Binutils 2.21, GCC 4.7.1 (mpfr 3.0.1, mpc 0.9, gmp 5.0.5), and Newlib 1.20.0.
The toolchain currently supports Big- and Little-Endian code as well as software floating point. Newlib C library stubs are left unchanged.