Minimal PDP8/L Implementation with 4K Disk Monitor System
Details
Category: Processor
Created: May 27, 2013
Updated: January 27, 2020
Language: VHDL
Other project properties
Development Status: Beta
Additional info: FPGA proven
WishBone compliant: No
WishBone version: n/a
License: LGPL
Description
This is an implementation of a Digital (DEC) PDP8/L processor with 4k memory, a single DF32 disk and serial interface. The project target is the ALTERA NEEK (Cyclone III EP3C25F324C6N). Run the 4K Disk Monitor System using only the FPGA chip. Download contains the complete Altera Quartus II (11.0) project directories with simulation files.
